Flexible static memory controller (FSMC)
Mode 1 - SRAM/CRAM
Figure 162. Mode1 read accesses
A[25:0]
NBL[1:0]
NEx
NOE
Memory transaction
RM0008
NWE
D[15:0]
High
data driven
by memory
(ADDSET +1)
HCLK cycles
(DATAST + 1)
HCLK cycles
2 HCLK
cycles
Data sampled Data strobe
ai14720c
Mode1 write accesses The one HCLK cycle at the end of the write transaction helps
Memory transaction
A[25:0]
NBL[1:0]
NEx
NOE
1HCLK
NWE
D[15:0]
(ADDSET +1)
HCLK cycles
data driven by FSMC
(DATAST + 1)
HCLK cycles
ai14721c
guarantee the address and data hold time after the NWE rising edge. Due to the presence
of this one HCLK cycle, the DATAST value must be greater than zero (DATAST > 0).
418/995
Doc ID 13902 Rev 9
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